The semiconductor industry has been able to maintain steady improvements of device performance by scaling of silicon-based devices. One such method of improving device performance has been the advent of finFETs. FinFETs are three dimensional (3D) devices, which include a plurality of gate structures spanning over a plurality of fins. FinFETs are capable of providing a multi-gate architecture for technology-scaling below 45 nm due to its exceptional control of Short Channel Effects (SCE) and its compatibility with standard CMOS processing.
FinFETs, though, lead to smaller silicon volume which may lead to device degradation due to inadequate heat dissipation, particularly when used with ESD devices. For example, ESD devices generate large quantities of heat due to the application of high currents and voltages. In conventional fabrication processes, the ESD devices are placed on a planar region of a substrate in order to adequately dissipate these high heat requirements into the substrate, itself. But to provide such a configuration in finFET technologies, special processes are required which leads to process integration complexity issues.